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YOKOHAMA, Japan--(BUSINESS WIRE)--Feb. 1, 2001-- Electronic Design and Solution Fair 2001--Virtual Silicon Technology, Inc. announced today that STARC, a consortium of 11 leading Japanese semiconductor design and manufacturing companies, has adopted its phase locked loop (PLL) technology for 0.13 micron technology as a leading benchmark for their initiative to improve IP reuse for System-On-Chip (SOC) design. Under the agreement, Virtual Silicon's eSi-PLL(TM) technology will be available and silicon proven on the common design rules for the 0.13 micron process jointly developed by leading semiconductor manufactures that include Fujitsu, Hitachi, Matsushita, NEC, Oki Electric, Rohm, Sanyo, Sharp, Sony and Toshiba.

``In today's SOC design, it is critical to have precise clocking schemes with PLLs to meet increasing performance targets,'' said Tadahiko Nakamura, senior manager IP Re-use Technology Group at STARC. ``Our initiative to develop a standard for IP re-use in 0.13-micron SOC designs in Japan will greatly benefit by having Virtual Silicon's PLL compiler technology available to our manufacturing partners.''

``Many of our high speed networking and communication customers are pushing the technology to maximize performance,'' said Tom Nukiyama, executive technical director, NEC Electronics, Inc. ``It is important for us to demonstrate high quality analog IP such as Virtual Silicon's PLL technology in order to meet these applications diverse needs on an open manufacturing standard.''

Silicon Proven PLL Circuit Design

The PLL circuit design has been proven with successful customer designs in several different 0.25, 0.18, 0.15 and 0.13-micron processes. The PLL operates in frequencies in excess of one gigahertz, and has demonstrated low jitter characteristics of less than 75 picoseconds.

Modular PLL Design Reduces Die Size and Increases Noise Immunity

The entire layout is designed to minimize die area by fitting inside the I/O pad ring, resulting in zero area usage in the core logic region. Utilizing proprietary technology licensed from Analog Bits, the analog components such as loop-filter, oscillator, by-pass circuitry are fully integrated and pre-connected to produce high-precision clock signals. The eSi-PLL technology incorporates a unique voltage-controlled oscillator (VCO) that offers excellent noise immunity and eliminates the need for external band-gap reference type circuitry.

``STARC's commitment to use eSi-PLL technology demonstrates Virtual Silicon's leadership in mixed-signal technology,'' said Mahesh Tirupattur, vice president Pacific Rim operations at Virtual Silicon. ``Our eSi-PLL technology offers a very unique solution that will greatly reduce time to market in future SOC designs.''

About Virtual Silicon Technology

Virtual Silicon Technology is a leading supplier of embedded semiconductor technology to manufacturers and designers of complex systems-on-chip. We provide process-intensive embedded components including standard cell libraries, I/Os, SRAM compilers, PLL compilers and embedded EEPROM solutions. The company provides application-specific, process-specific and foundry-portable versions of its Silicon Ready libraries and hard IP to semiconductor manufacturers and foundries, ASSP designers, and systems developers who demand the highest quality, maximum performance and optimum densities for their semiconductor innovations. For more information on Virtual Silicon Technology and its products, please direct customer inquiries to Mahesh Tirupattur at (408) 548-2726, email address: mahesh@virtual-silicon.com or go to www.virtual-silicon.com.

eSilicon, eSi-Route, eSi-Pad, eSi-RAM, eSi-ROM, eSi-PLL, The Heart of Great Silicon, Silicon Ready, IP Ambassador, Design Service Ambassador, and Virtual Silicon are trademarks of Virtual Silicon Technology, Inc.

     Virtual Silicon Technology
     Mahesh Tirupattur, 408/548-2726
     mahesh@virtual-silicon.com
      or
     VitalCom Marketing and PR
     Karen Tyrrell, 650/637-8212 Ext. 204
     karen@vitalcompr.com